Static Timing Analysis

Project : SimpleSDR_PSoC
Build Time : 03/16/12 15:22:24
Device : CY8C3866PVI-021
Temperature : -40C - 85C
Vio0 : 3.3
Vio1 : 3.3
Vio2 : 3.3
Vio3 : 3.3
Voltage : 3.3
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyBUS_CLK Clock_FracN -32.579
CyBUS_CLK CyBUS_CLK -3.821
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk Sync 12.000 MHz 14.000 MHz N/A
ADC_theACLK Sync 6.000 MHz 6.222 MHz N/A
ClockBlock/aclk_0 Async 6.000 MHz 6.000 MHz N/A
ClockBlock/clk_bus Async 56.000 MHz 56.000 MHz N/A
ClockBlock/dclk_0 Async 2.667 MHz 2.667 MHz N/A
ClockBlock/dclk_1 Async 12.000 MHz 12.000 MHz N/A
Clock_FracN Sync 2.667 MHz 2.667 MHz 18.749 MHz
CyBUS_CLK Sync 56.000 MHz 56.000 MHz 19.827 MHz Frequency
CyILO Async 100.000 kHz 100.000 kHz N/A
CyIMO Async 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK Sync 56.000 MHz 56.000 MHz N/A
CyPLL_OUT Async 56.000 MHz 56.000 MHz N/A
CyXTAL Async 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 375ns(2.66667 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt0_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt0_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt0_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt0_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.749 MHz 53.337 321.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.750 MHz 53.334 321.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/cout 0.800
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_7:g1:a0:s_2\/cout \FracN:MODULE_7:g1:a0:s_3\/cin 0.000
macrocell14 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/cin \FracN:MODULE_7:g1:a0:s_3\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/q_fixed \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 2.911
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 \FracN:MODULE_8:g1:a0:s_3\/cout 3.830
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:acc1_0\/q \FracN:MODULE_8:g1:a0:s_6\/cin 18.750 MHz 53.334 321.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \FracN:acc1_0\ \FracN:acc1_0\/clock_0 \FracN:acc1_0\/q 1.250
Route 1 \FracN:acc1_0\ \FracN:acc1_0\/q \FracN:adder1_0\/cpt1_1 6.530
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_1 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/cout 0.800
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_7:g1:a0:s_2\/cout \FracN:MODULE_7:g1:a0:s_3\/cin 0.000
macrocell14 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/cin \FracN:MODULE_7:g1:a0:s_3\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/q_fixed \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 2.911
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 \FracN:MODULE_8:g1:a0:s_3\/cout 3.830
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
Path Delay Requirement : 17.8571ns(56 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt0_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt0_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt0_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt0_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt0_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt0_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.827 MHz 50.436 -32.579 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/q_fixed \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 2.914
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ \FracN:MODULE_8:g1:a0:s_2\/cpt1_1 \FracN:MODULE_8:g1:a0:s_2\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_8:g1:a0:s_2\/cout \FracN:MODULE_8:g1:a0:s_3\/cin 0.000
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cin \FracN:MODULE_8:g1:a0:s_3\/cout 1.130
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.828 MHz 50.433 -32.576 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt0_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/cout 0.800
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_7:g1:a0:s_2\/cout \FracN:MODULE_7:g1:a0:s_3\/cin 0.000
macrocell14 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/cin \FracN:MODULE_7:g1:a0:s_3\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/q_fixed \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 2.911
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 \FracN:MODULE_8:g1:a0:s_3\/cout 3.830
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
\FracN:FracLo\/control_0 \FracN:MODULE_8:g1:a0:s_6\/cin 19.828 MHz 50.433 -32.576 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \FracN:FracLo\ \FracN:FracLo\/busclk \FracN:FracLo\/control_0 2.580
Route 1 \FracN:frac_0\ \FracN:FracLo\/control_0 \FracN:adder1_0\/cpt1_0 2.299
macrocell53 U(2,4) 1 \FracN:adder1_0\ \FracN:adder1_0\/cpt1_0 \FracN:adder1_0\/cout 3.500
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:adder1_0\/cout \FracN:adder1_1\/cin 0.000
macrocell59 U(2,4) 1 \FracN:adder1_1\ \FracN:adder1_1\/cin \FracN:adder1_1\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:adder1_1\/cout \FracN:adder1_2\/cin 0.000
macrocell60 U(2,4) 1 \FracN:adder1_2\ \FracN:adder1_2\/cin \FracN:adder1_2\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:adder1_2\/cout \FracN:adder1_3\/cin 0.000
macrocell61 U(2,4) 1 \FracN:adder1_3\ \FracN:adder1_3\/cin \FracN:adder1_3\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:adder1_3\/cout \FracN:adder1_4\/cin 0.000
macrocell62 U(2,3) 1 \FracN:adder1_4\ \FracN:adder1_4\/cin \FracN:adder1_4\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:adder1_4\/cout \FracN:adder1_5\/cin 0.000
macrocell63 U(2,3) 1 \FracN:adder1_5\ \FracN:adder1_5\/cin \FracN:adder1_5\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:adder1_5\/cout \FracN:adder1_6\/cin 0.000
macrocell64 U(2,3) 1 \FracN:adder1_6\ \FracN:adder1_6\/cin \FracN:adder1_6\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_6\ \FracN:adder1_6\/cout \FracN:adder1_7\/cin 0.000
macrocell65 U(2,3) 1 \FracN:adder1_7\ \FracN:adder1_7\/cin \FracN:adder1_7\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_7\ \FracN:adder1_7\/cout \FracN:adder1_8\/cin 0.000
macrocell66 U(2,3) 1 \FracN:adder1_8\ \FracN:adder1_8\/cin \FracN:adder1_8\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_8\ \FracN:adder1_8\/cout \FracN:adder1_9\/cin 0.000
macrocell67 U(2,3) 1 \FracN:adder1_9\ \FracN:adder1_9\/cin \FracN:adder1_9\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_9\ \FracN:adder1_9\/cout \FracN:adder1_10\/cin 0.000
macrocell54 U(2,3) 1 \FracN:adder1_10\ \FracN:adder1_10\/cin \FracN:adder1_10\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_10\ \FracN:adder1_10\/cout \FracN:adder1_11\/cin 0.000
macrocell55 U(2,3) 1 \FracN:adder1_11\ \FracN:adder1_11\/cin \FracN:adder1_11\/cout 1.130
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_11\ \FracN:adder1_11\/cout \FracN:adder1_12\/cin 0.000
macrocell56 U(3,3) 1 \FracN:adder1_12\ \FracN:adder1_12\/cin \FracN:adder1_12\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_12\ \FracN:adder1_12\/cout \FracN:adder1_13\/cin 0.000
macrocell57 U(3,3) 1 \FracN:adder1_13\ \FracN:adder1_13\/cin \FracN:adder1_13\/cout 0.800
Route 1 \FracN:MODULE_4:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_13\ \FracN:adder1_13\/cout \FracN:adder1_14\/cin 0.000
macrocell58 U(3,3) 1 \FracN:adder1_14\ \FracN:adder1_14\/cin \FracN:adder1_14\/q_fixed 2.030
Route 1 \FracN:adder1_14\ \FracN:adder1_14\/q_fixed \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 2.911
macrocell4 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_0\ \FracN:MODULE_6:g1:a0:s_0\/cpt1_0 \FracN:MODULE_6:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_6:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_6:g1:a0:s_0\/cout \FracN:MODULE_6:g1:a0:s_1\/cin 0.000
macrocell5 U(3,2) 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/cin \FracN:MODULE_6:g1:a0:s_1\/q_fixed 2.030
Route 1 \FracN:MODULE_6:g1:a0:s_1\ \FracN:MODULE_6:g1:a0:s_1\/q_fixed \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 3.662
macrocell12 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_1\ \FracN:MODULE_7:g1:a0:s_1\/cpt1_0 \FracN:MODULE_7:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_7:g1:a0:s_1\/cout \FracN:MODULE_7:g1:a0:s_2\/cin 0.000
macrocell13 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_2\ \FracN:MODULE_7:g1:a0:s_2\/cin \FracN:MODULE_7:g1:a0:s_2\/cout 0.800
Route 1 \FracN:MODULE_7:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_2\ \FracN:MODULE_7:g1:a0:s_2\/cout \FracN:MODULE_7:g1:a0:s_3\/cin 0.000
macrocell14 U(3,4) 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/cin \FracN:MODULE_7:g1:a0:s_3\/q_fixed 2.030
Route 1 \FracN:MODULE_7:g1:a0:s_3\ \FracN:MODULE_7:g1:a0:s_3\/q_fixed \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 2.911
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ \FracN:MODULE_8:g1:a0:s_3\/cpt0_1 \FracN:MODULE_8:g1:a0:s_3\/cout 3.830
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_3\ \FracN:MODULE_8:g1:a0:s_3\/cout \FracN:MODULE_8:g1:a0:s_4\/cin 0.000
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ \FracN:MODULE_8:g1:a0:s_4\/cin \FracN:MODULE_8:g1:a0:s_4\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_4\ \FracN:MODULE_8:g1:a0:s_4\/cout \FracN:MODULE_8:g1:a0:s_5\/cin 0.000
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ \FracN:MODULE_8:g1:a0:s_5\/cin \FracN:MODULE_8:g1:a0:s_5\/cout 0.800
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_5\ \FracN:MODULE_8:g1:a0:s_5\/cout \FracN:MODULE_8:g1:a0:s_6\/cin 0.000
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ SETUP 2.190
Clock Skew 0.000
Path Delay Requirement : 17.8571ns(56 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\IQ_Generator:IQDividerMax\/control_3 Net_1089/main_4 46.130 MHz 21.678 -3.821 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_3 2.580
Route 1 \IQ_Generator:divMax_3\ \IQ_Generator:IQDividerMax\/control_3 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_0 3.295
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_0 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_1 Net_1089/main_4 47.217 MHz 21.179 -3.322 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_1 2.580
Route 1 \IQ_Generator:divMax_1\ \IQ_Generator:IQDividerMax\/control_1 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_2 2.796
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_2 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:divider_2\/q Net_1089/main_4 47.344 MHz 21.122 -3.265 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell87 U(2,1) 1 \IQ_Generator:divider_2\ \IQ_Generator:divider_2\/clock_0 \IQ_Generator:divider_2\/q 1.250
Route 1 \IQ_Generator:divider_2\ \IQ_Generator:divider_2\/q \IQ_Generator:MODULE_1:g1:a0:xeq\/main_5 4.069
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_5 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_2 Net_1089/main_4 47.621 MHz 20.999 -3.142 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_2 2.580
Route 1 \IQ_Generator:divMax_2\ \IQ_Generator:IQDividerMax\/control_2 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_1 2.616
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_1 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_0 Net_1089/main_4 48.333 MHz 20.690 -2.833 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_0 2.580
Route 1 \IQ_Generator:divMax_0\ \IQ_Generator:IQDividerMax\/control_0 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_3 2.307
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_3 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:divider_0\/q Net_1089/main_4 48.471 MHz 20.631 -2.774 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/clock_0 \IQ_Generator:divider_0\/q 1.250
Route 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/q \IQ_Generator:MODULE_1:g1:a0:xeq\/main_7 3.578
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_7 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:divider_1\/q Net_1089/main_4 49.015 MHz 20.402 -2.545 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/clock_0 \IQ_Generator:divider_1\/q 1.250
Route 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/q \IQ_Generator:MODULE_1:g1:a0:xeq\/main_6 3.349
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_6 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:divider_3\/q Net_1089/main_4 50.113 MHz 19.955 -2.098 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ \IQ_Generator:divider_3\/clock_0 \IQ_Generator:divider_3\/q 1.250
Route 1 \IQ_Generator:divider_3\ \IQ_Generator:divider_3\/q \IQ_Generator:MODULE_1:g1:a0:xeq\/main_4 2.902
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_4 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1089_split/main_9 3.295
macrocell3 U(2,1) 1 Net_1089_split Net_1089_split/main_9 Net_1089_split/q 3.350
Route 1 Net_1089_split Net_1089_split/q Net_1089/main_4 2.298
macrocell2 U(2,1) 1 Net_1089 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_3 Net_1087/main_0 57.009 MHz 17.541 0.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_3 2.580
Route 1 \IQ_Generator:divMax_3\ \IQ_Generator:IQDividerMax\/control_3 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_0 3.295
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_0 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1087/main_0 4.806
macrocell1 U(3,3) 1 Net_1087 SETUP 3.510
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_1 Net_1087/main_0 58.679 MHz 17.042 0.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_1 2.580
Route 1 \IQ_Generator:divMax_1\ \IQ_Generator:IQDividerMax\/control_1 \IQ_Generator:MODULE_1:g1:a0:xeq\/main_2 2.796
macrocell84 U(3,1) 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/main_2 \IQ_Generator:MODULE_1:g1:a0:xeq\/q 3.350
Route 1 \IQ_Generator:MODULE_1:g1:a0:xeq\ \IQ_Generator:MODULE_1:g1:a0:xeq\/q Net_1087/main_0 4.806
macrocell1 U(3,3) 1 Net_1087 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_0\/main_0 4.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_0\/main_0 3.158
macrocell18 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_0\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_1\/main_0 4.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_1\/main_0 3.158
macrocell19 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_1\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_2\/main_0 4.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_2\/main_0 3.158
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_3\/main_0 4.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_3\/main_0 3.158
macrocell21 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_3\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_4\/main_0 5.755
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_4\/main_0 4.505
macrocell22 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_4\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_5\/main_0 5.755
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_5\/main_0 4.505
macrocell23 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_5\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_6\/main_0 5.755
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_6\/main_0 4.505
macrocell24 U(3,4) 1 \FracN:MODULE_8:g1:a0:s_6\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_1\/cin 7.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_0\/cpt0_0 3.158
macrocell18 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_0\ \FracN:MODULE_8:g1:a0:s_0\/cpt0_0 \FracN:MODULE_8:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_8:g1:a0:s_0\/cout \FracN:MODULE_8:g1:a0:s_1\/cin 0.000
macrocell19 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_1\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_1\/cin 7.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_0\/cpt1_0 3.158
macrocell18 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_0\ \FracN:MODULE_8:g1:a0:s_0\/cpt1_0 \FracN:MODULE_8:g1:a0:s_0\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_0\ \FracN:MODULE_8:g1:a0:s_0\/cout \FracN:MODULE_8:g1:a0:s_1\/cin 0.000
macrocell19 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_1\ HOLD 0.000
Clock Skew 0.000
\FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_2\/cin 7.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,5) 1 \FracN:minus1\ \FracN:minus1\/clock_0 \FracN:minus1\/q 1.250
Route 1 \FracN:minus1\ \FracN:minus1\/q \FracN:MODULE_8:g1:a0:s_1\/cpt0_0 3.158
macrocell19 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_1\ \FracN:MODULE_8:g1:a0:s_1\/cpt0_0 \FracN:MODULE_8:g1:a0:s_1\/cout 3.500
Route 1 \FracN:MODULE_8:g1:a0:g0:u0:gof:g_arith(0):ga:cadd_1\ \FracN:MODULE_8:g1:a0:s_1\/cout \FracN:MODULE_8:g1:a0:s_2\/cin 0.000
macrocell20 U(3,5) 1 \FracN:MODULE_8:g1:a0:s_2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\FracN:FracHi\/control_7 \FracN:acc1_4\/main_0 5.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_4\/main_0 3.535
macrocell33 U(3,3) 1 \FracN:acc1_4\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_5\/main_0 5.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_5\/main_0 3.535
macrocell34 U(3,3) 1 \FracN:acc1_5\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_6\/main_0 5.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_6\/main_0 3.535
macrocell35 U(3,3) 1 \FracN:acc1_6\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_7\/main_0 5.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_7\/main_0 3.535
macrocell36 U(3,3) 1 \FracN:acc1_7\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_13\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_13\/main_0 4.630
macrocell29 U(2,2) 1 \FracN:acc1_13\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_1\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_1\/main_0 4.630
macrocell30 U(2,2) 1 \FracN:acc1_1\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_2\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_2\/main_0 4.630
macrocell31 U(2,2) 1 \FracN:acc1_2\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_3\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_3\/main_0 4.630
macrocell32 U(2,2) 1 \FracN:acc1_3\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_10\/main_0 6.684
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_10\/main_0 4.644
macrocell26 U(2,2) 1 \FracN:acc1_10\ HOLD 0.000
Clock Skew 0.000
\FracN:FracHi\/control_7 \FracN:acc1_11\/main_0 7.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \FracN:FracHi\ \FracN:FracHi\/busclk \FracN:FracHi\/control_7 2.040
Route 1 \FracN:resetAcc\ \FracN:FracHi\/control_7 \FracN:acc1_11\/main_0 5.338
macrocell27 U(2,4) 1 \FracN:acc1_11\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\IQ_Generator:divider_3\/q \IQ_Generator:divider_3\/main_0 4.152
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ \IQ_Generator:divider_3\/clock_0 \IQ_Generator:divider_3\/q 1.250
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ \IQ_Generator:divider_3\/q \IQ_Generator:divider_3\/main_0 2.902
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_1\/q \IQ_Generator:divider_1\/main_0 4.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/clock_0 \IQ_Generator:divider_1\/q 1.250
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/q \IQ_Generator:divider_1\/main_0 3.091
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_1\/q \IQ_Generator:divider_2\/main_1 4.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/clock_0 \IQ_Generator:divider_1\/q 1.250
Route 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/q \IQ_Generator:divider_2\/main_1 3.353
macrocell87 U(2,1) 1 \IQ_Generator:divider_2\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_1\/q \IQ_Generator:divider_3\/main_2 4.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/clock_0 \IQ_Generator:divider_1\/q 1.250
Route 1 \IQ_Generator:divider_1\ \IQ_Generator:divider_1\/q \IQ_Generator:divider_3\/main_2 3.353
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_0\/q \IQ_Generator:divider_0\/main_0 4.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/clock_0 \IQ_Generator:divider_0\/q 1.250
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/q \IQ_Generator:divider_0\/main_0 3.410
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_0\/q \IQ_Generator:divider_2\/main_2 4.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/clock_0 \IQ_Generator:divider_0\/q 1.250
Route 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/q \IQ_Generator:divider_2\/main_2 3.410
macrocell87 U(2,1) 1 \IQ_Generator:divider_2\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_0\/q \IQ_Generator:divider_3\/main_3 4.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/clock_0 \IQ_Generator:divider_0\/q 1.250
Route 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/q \IQ_Generator:divider_3\/main_3 3.410
macrocell88 U(2,1) 1 \IQ_Generator:divider_3\ HOLD 0.000
Clock Skew 0.000
\IQ_Generator:divider_0\/q \IQ_Generator:divider_1\/main_1 4.698
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(2,1) 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/clock_0 \IQ_Generator:divider_0\/q 1.250
Route 1 \IQ_Generator:divider_0\ \IQ_Generator:divider_0\/q \IQ_Generator:divider_1\/main_1 3.448
macrocell86 U(3,1) 1 \IQ_Generator:divider_1\ HOLD 0.000
Clock Skew 0.000
Net_1089/q Net_1089/main_1 5.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,1) 1 Net_1089 Net_1089/clock_0 Net_1089/q 1.250
macrocell2 U(2,1) 1 Net_1089 Net_1089/q Net_1089/main_1 3.975
macrocell2 U(2,1) 1 Net_1089 HOLD 0.000
Clock Skew 0.000
\IQ_Generator:IQDividerMax\/control_3 Net_1089/main_2 5.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,1) 1 \IQ_Generator:IQDividerMax\ \IQ_Generator:IQDividerMax\/busclk \IQ_Generator:IQDividerMax\/control_3 2.040
Route 1 \IQ_Generator:divMax_3\ \IQ_Generator:IQDividerMax\/control_3 Net_1089/main_2 3.309
macrocell2 U(2,1) 1 Net_1089 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Net_1089/q QCLK(0)_PAD 24.822
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,1) 1 Net_1089 Net_1089/clock_0 Net_1089/q 1.250
Route 1 Net_1089 Net_1089/q QCLK(0)/pin_input 6.572
sio P12[2] 1 QCLK(0) QCLK(0)/pin_input QCLK(0)/pad_out 17.000
Route 1 QCLK(0)_PAD QCLK(0)/pad_out QCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1087/q ICLK(0)_PAD 23.729
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,3) 1 Net_1087 Net_1087/clock_0 Net_1087/q 1.250
Route 1 Net_1087 Net_1087/q ICLK(0)/pin_input 5.479
sio P12[3] 1 ICLK(0) ICLK(0)/pin_input ICLK(0)/pad_out 17.000
Route 1 ICLK(0)_PAD ICLK(0)/pad_out ICLK(0)_PAD 0.000
Clock Clock path delay 0.000